FIG. 4 shows a conventional master-slave type flip-flop circuit. This master-slave type flip-flop circuit is structured by a master flip-flop MF' and a slave flip-flop SF'Transistors used in this circuit are of npn-type.
The master flip-flop MF' is structured by a differential circuit 101 for taking in input signals D and DB, a differential circuit 102 as an input stage of clocks T and TB (TB may be a reference voltage at which a high potential H level and a low potential L level of a T signal can be detected) connected in cascade to the differential circuit 101, and a potential-setting circuit RL101 for determining levels of data lines L101 and L102.
The differential circuit 101 has transistors Q101 and Q102 having collectors connected in common, and transistors Q103 and Q104 having collectors connected in common. These transistors Q101, Q102, Q103 and Q104 constitute an ECL for collectors of transistors Q105 and Q106 of the differential circuit 102. The input signals D and DB are applied to the bases of the transistors Q101 and Q104 respectively. The base of the transistor Q102 is connected to a collector common connection line of the transistors Q103 and Q104, and the base of the transistor Q103 is connected to a collector common connection line of the transistors Q101 and Q102.
The transistors Q105 and Q106 of the differential circuit 102 constitute an ECL for the collector of the transistor Q113, with clocks T and TB supplied to respective bases of these transistors Q105 and Q106. The transistor Q113 has an emitter grounded through an emitter resistor RE, and is constantly kept in an ON state due to a voltage VCB applied to the base.
The slave flip-flop SF' is structured by a differential circuit 103 for taking in signals obtained from the data lines L101 and L102, a differential circuit 104 as an input stage of clocks T and TB connected in cascade to the differential circuit 103, and a potential-setting circuit RL102 for determining levels of output signals Q and QB.
The differential circuit 103 has transistors Q107 and Q108 having collectors connected in common, and transistors Q109 and Q110 having collectors connected in common. These transistors Q107, Q108, Q109 and Q110 constitute an ECL for collectors of transistors Q11 and Q112 of the differential circuit 104.
The transistor Q107 has its base connected to the collector common connection line of the transistors Q101 and Q102 by the data line L101. The transistor Q110 has its base connected to the collector common connection line of the transistors Q103 and Q104 by the data line L102. The transistor Q108 has its base connected to a collector common connection line of the transistors Q109 and Q110. Similarly, the transistor Q109 has its base connected to a collector common connection line of the transistors Q107 and Q108. An output signal Q is taken out from the collector common connection line of the transistors Q107 and Q108. Similarly, an output signal QB is taken out from the collector common connection line of the transistors Q109 and Q110.
The transistors Q111 and Q112 of the differential circuit 104 constitute an ECL for the collector of a transistor Q114, with clocks T and TB supplied to respective bases of these transistors Q111 and Q112. The transistor Q114 has an emitter grounded through an emitter resistor RE, and is constantly kept in an ON state due to a voltage VCB applied to the base.
According to the master-slave type flip-flop circuit having the ECL structure as described above, as shown in FIG. 5, an output signal terminal (QB) and an input signal terminal (D) are short-circuited, and an output signal terminal (Q) and an input signal terminal (DB) are short-circuited. Therefore, the master-slave type flip-flop circuit operates as a frequency-dividing circuit.
Next, the operation of the frequency-dividing circuit formed by the line connection shown in FIG. 5 will be explained in four stages with reference to an input and output waveform diagram shown in FIG. 6.
At first, (1) in FIG. 6 is assumed as a first stage. When a clock T has changed from a high potential H to a low potential L, and when a clock TB has changed from a low potential L to a high potential H, the transistor Q105 of the differential circuit 102 changes from OFF to ON, the transistor Q106 changes from ON to OFF, the transistor Q111 of the differential circuit 104 changes from OFF to ON, and the transistor Q112 changes from ON to OFF.
Along with the change in the state of the differential circuit 102, the transistor Q101 of the differential circuit 101 changes from ON to OFF, the transistor Q102 changes from OFF to ON, the transistors Q103 and Q104 keep OFF state, the data line L101 keeps a low potential L, and the data line L102 keeps a high potential H, and data is held in this state.
Further, along with the change in the state of the differential circuit 104, the transistor Q107 of the differential circuit 103 keeps an OFF status, the transistor Q108 changes from ON to OFF, the transistor Q109 keeps OFF state, the transistor Q110 changes from OFF to ON, the output Q changes from a low potential L to a high potential H, and the output QB changes from a high potential H to a low potential L. Along with the changes in the status of the outputs Q and QB, the base potential of the transistor Q101 changes from a high potential H to a low potential L, and the base potential of the transistor Q104 changes from a low potential L to a high potential H.
Next, (2) in FIG. 6 is assumed as a second stage. When the clock T has changed from the low potential L to a high potential H, and when the clock TB has changed from the high potential H to a low potential L, the transistor Q105 of the differential circuit 102 changes from ON to OFF, the transistor Q106 changes from OFF to ON, the transistor Q11 of the differential circuit 104 changes from ON to OFF, and the transistor Q112 changes from OFF to ON.
Along with the change in the status of the differential circuit 102, the transistor Q101 of the differential circuit 101 keeps OFF state, the transistor Q102 changes from ON to OFF, the transistor Q103 keeps OFF state, and the transistor Q104 changes from OFF to ON, the data line L101 changes from the low potential L to a high potential H, and the data line L102 changes from a high potential H to a low potential L.
Further, along with the change in the state of the differential circuit 104, the transistors Q107 and Q108 of the differential circuit 103 keep OFF state, the transistor Q109 changes from OFF to ON, the transistor Q110 changes from ON to OFF, the output Q keeps the high potential H, and the output QB keeps the low potential L. Along with the changes in the state of the data lines L101 and L102, the base potential of the transistor Q107 changes to a low potential L, and the base potential of the transistor Q110 changes to a high potential H.
Next, (3) in FIG. 6 is assumed as a third stage. When the clock T has changed from the high potential H to a low potential L, and when the clock TB has changed from the low potential L to a high potential H, the transistor Q105 of the differential circuit 102 changes from OFF to ON, the transistor Q106 changes from ON to OFF, the transistor Q11 of the differential circuit 104 changes from OFF to ON, and the transistor Q112 changes from ON to OFF.
Along with the change in the status of the differential circuit 102, the transistors Q101 and Q102 of the differential circuit 101 keep OFF state, the transistor Q103 changes from OFF to ON, and the transistor Q104 changes from ON to OFF, the data line L101 keeps the high potential H, and the data line L102 keeps the L potential.
Further, along with the change in the state of the differential circuit 104, the transistor Q107 of the differential circuit 103 changes from OFF to ON, the transistor Q108 keeps OFF state, the transistor Q109 changes from ON to OFF, the transistor Q110 keeps OFF state, the output Q change from the high potential H to a low potential L, and the output QB changes from the low potential L to a high potential H. Along with the changes in the status of the outputs Q and QB, the base potential of the transistor Q101 changes from the low potential L to a high potential H, and the base potential of the transistor Q104 changes from the high potential H to a low potential L.
Next, (4) in FIG. 6 is assumed as a fourth stage. When the clock T has changed from the low potential L to a high potential H, and when the clock TB has changed from the high potential H to a low potential L, the transistor Q105 of the differential circuit 102 changes from ON to OFF, the transistor Q106 changes from OFF to ON, the transistor Q111 of the differential circuit 104 changes from ON to OFF, and the transistor Q112 changes from OFF to ON.
Along with the change in the state of the differential circuit 102, the transistor Q101 of the differential circuit 101 changes from OFF to ON, the transistor Q102 keeps OFF state, the transistor Q103 changes from ON to OFF, and the transistor Q104 keeps OFF state, the data line L101 changes from the high potential H to a low potential L, and the data line L102 changes from the L potential to a high potential H.
Further, along with the change in the state of the differential circuit 104, the transistor Q107 of the differential circuit 103 changes from ON to OFF, the transistor Q108 changes from OFF to ON, the transistors Q109 and Q110 keep OFF state, the output Q keeps the low potential L, and the output QB keeps the high potential H. Along with the changes in the state of the data lines L101 and L102, the base potential of the transistor Q107 changes to a high potential H, and the base potential of the transistor Q110 changes to a low potential L.
By repeating the operation of above-described stages (1) to (4), the conventional circuit has been utilized as a frequency-dividing circuit.
As a further example of the conventional master-slave type flip-flop circuit, there has been known a system for carrying out a passing and interrupting of data signals, by parallel connecting a pair of clock input differential units and a pair of data input latch differential units, and by applying a clock signal to the bases of the transistors of the pair of data input latch differential units, as disclosed in Japanese Patent Application Laid-open No. HEI 9-266435 and Japanese Patent Application Laid-open No. HEI 10-51278.
According to the prior-art master-slave type flip-flop circuit shown in FIG. 4 and FIG. 5, the transistors between the power supply and the ground in a semiconductor integrated circuit are constructed in three stages in cascade connection. Accordingly, as a minimum operation power supply voltage, a voltage of 2Vbe (a voltage between the base and the emitter) plus Vsat (a saturation voltage between the collector and the emitter) plus a constant current emitter resistance voltage drop (IE.times.RE) is at least required. If the power supply voltage is lower than this then there a problem that the flip-flops cannot operate.
In general, portable communication devices such as portable telephones and PHSs (Personal Handiphone Systems) are operated by using batteries as a power source. Therefore, when the prior-art master-slave type flip-flop circuit as shown in FIG. 4 and FIG. 5 is used as a circuit for frequency-dividing a high-frequency signal, this circuit requires a large power consumption because of its high minimum operation power supply voltage. Therefore, it is not possible to make call time and wait time longer.
In order to solve the above problems, in the above-described conventional master-slave type flip-flop circuit, an attempt has been made to lower the power supply voltage by decreasing a logical amplitude voltage (VM) and the constant current voltage drop (IE.times.RE). However, as the transistors between the power supply VCC and the ground GND in the semiconductor integrated circuit are constructed in three stages in cascade connection, it is not possible to drive the circuit at a low voltage of 2 V or below. Therefore, there has been a limit to the reduction in power consumption.
The master-slave type flip-flop circuit as disclosed in Japanese Patent Application Laid-open No. 9-266435 and Japanese Patent Application Laid-open No. 10-51278 has a parallel connection of the pair of clock input differential units and the pair of data input latch differential units. Therefore, as compared with the prior-art master-slave type flip-flop circuit as shown in FIG. 4 and FIG. 5, the minimum operation power supply voltage is lower and the circuit can be driven at a low voltage of 2 V or below. However, there is a limit to increasing the operation speed because of the circuit structure.